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FUJITSU SEMICONDUCTOR DATA SHEET
16-bit Proprietary Microcontroller
CMOS
R
MB90335 Series
MB90337/F337/V330A
s DESCRIPTION
The MB90335 series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB feature supports not only 12-Mbps Function operation but also MiniHost operation. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. While inheriting the AT architecture of the F2MC* family, the instruction set supports the C language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, long word processing is now available by introducing a 32-bit accumulator. * : F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
s FEATURES
* Clock * Built-in oscillation circuit and PLL clock frequency multiplication circuit * Oscillation clock The machine clock is the oscillation clock divided into 2 (for oscillation 6 MHz : 3 MHz) Clock for USB is 48 MHz Machine clock frequency of 6 MHz, 12 MHz or 24 MHz selectable * Minimum execution time of instruction : 41.6 ns (6 MHz oscillation clock, 4-time multiplied : machine clock 24 MHz and at operating VCC = 3.3 V) * The maximum memory space:16 MB * 24-bit addressing * Bank addressing
(Continued)
64-pin plastic LQFP
s PACKAGE
(FPT-64P-M09)
MB90335 Series
(Continued)
* Instruction system Data types: Bit, Byte, Word, Long word Addressing mode (23 types) Enhanced high-precision computing with 32-bit accumulator Enhance Multiply/Divide instructions with sign and the RETI instruction * Instruction system compatible with high-level language (C language) and multitask * Employing system stack pointer * Instruction set symmetry and barrel shift instructions * Program Patch Function (2 address pointer) * 4-byte instruction queue * Interrupt function * Priority levels are programmable * 20 interrupts * Data transfer function * Expanded intelligent I/O service function (EI2OS) : Maximum of 16 channels * DMAC : Maximum 16 channels * Low Power Consumption Mode * Sleep mode (with the CPU operating clock stopped) * Time - base timer mode (with the oscillator clock and time - base timer operating) * Stop mode (with the oscillator clock stopped) * CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles) * Package * LQFP-64P (FPT-64P-M09 : 0.65 mm pin pitch) * Process : CMOS technology * Operation guaranteed temperature: -40 C to +85 C (0 C to +70 C when USB is in use)
2
MB90335 Series
s INTERNAL PERIPHERAL FUNCTION (RESOURCE)
* I/O port: Max 45 ports * Time-base timer : 1channel * Watchdog timer : 1 channel * 16-bit reload timer : 1 channel * Multi-functional timer * 8/16-bit PPG timer (8-bit x 4 channels or 16-bit x 2 channels) the period and duty of the output pulse can be set by the program. * 16-bit PWC timer : 1 channel Timer function and pulse width measurement function * UART : 2 channels * Equipped with Full duplex double buffer with 8-bit lenghth * Asynchronous transfer or clock-synchronous serial (I/O extended serial) transfer can be set. * Extended I/O serial interface: 1 channel * DTP/External interrupt circuit (8 channels) * Activate the extended intelligent I/O service by external interrupt input * Interrupt output by external interrupt input * Delayed interrupt output module * Output an interrupt request for task switching * USB : 1 channel * USB function (conform to USB 2.0 Full Speed) * Supports for Full Speed/Endpoint are specifiable up to six. * Dual port RAM (The FIFO mode is supported). * Transfer type: Control, Interrupt, Bulk or Isochronous transfer possible * USB Mini Host function * I2C Interface : 1 channel * Supports Intel SM bus standards and Phillips I2C bus standards * Two-wire data transfer protocol specification * Master and slave transmission/reception Note : I2C licenae : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Phillips.
3
MB90335 Series
s PRODUCT LINEUP
1. MB90335 Series
Part number Type ROM capacity RAM capacity Emulator-specific power supply * MB90V330A For evaluation No 28 Kbyte Used bit Number of basic instructions Minimum instruction execution time Addressing type Program Patch Function maximum memory space I/O Ports(CMOS) 45 ports Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable. It can also be used for I/O serial. Built-in special baud-rate generator Built-in 2 channels 16-bit reload timer operation Built-in 1 channel 8/16-bit PPG timer (8-bit mode x 4 channels, 16-bit mode x 2 channels) 16-bit PWC timer x 1 channel 8 channels Interrupt factor : "L""H" edge /"H""L" edge /"L" level /"H" level selectable 1 channel 1 channel 1 channel USB function (conform to USB 2.0 Full Speed) USB Mini-HOST function 6 ports (Excluding VBUS and I/O for I2C) Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode CMOS 3.3 V 0.3 V (at maximum machine clock 24 MHz) MB90F337 Built-in FLASH MEMORY 4 Kbyte : 351 instructions : 41.6 ns / at oscillation of 6 MHz (When 4 times is used : Machine clock of 24 MHz) : 23 types : For two address pointers : 16 Mbyte 64 Kbyte MB90337 Built-in Mask ROM
CPU functions
Ports
UART
16-bit reload timer Multi-functional timer DTP/External interrupt I2C Extended I/O serial interface USB Withstand voltage of 5 V Low Power Consumption Mode Process Operating voltage VCC
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB214701 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
s PACKAGES AND PRODUCT MODELS
Package FPT-64P-M09 (LQFP-0.65 mm) PGA-299C-A01 (PGA) : Yes x : No x x MB90337 MB90F337 MB90V330A x
Note : For detailed information on each package, see "s PACKAGE DIMENSIONS". 4
s PIN ASSIGNMENT
VBUS Vss DVM DVP Vcc Vss HVM HVP Vcc HCONX P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(TOP VIEW)
(FPT-64P-M09)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Vss X1 X0 P24/PPG0 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10
P52 P53 Vss MD2 MD1 MD0 RST P54 P00 P01 P02 P03 P04 P05 P06 P07
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P51 P41/TOT0 P40/TIN0 P67/INT7/SDA0 P66/INT6/SCL0 P65/INT5/PWC P64/INT4/SCK P63/INT3/SOT P62/INT2/SIN P61/INT1 P60/INT0 P27/PPG3 P26/PPG2 P25/PPG1 P50 Vcc
MB90335 Series
5
MB90335 Series
s PIN DESCRIPTION
Pin no. QFPM09 46 , 47 23 25 to 32 Pin name Circuit type* A F I Status at reset/ function Function
X0, X1 RST P00 to P07
It is a terminal which connects the oscillator. Oscillation When connecting an external clock, leave the X1 pin side unconstatus nected. Reset input External reset input pin. General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD00 to RD07 = 1) by the pull-up resistor setting register (RDR0). (When the power output is set, it is invalid.) General purpose input/output port. The ports can be set to be added with a pull-up resistor (RD10 to RD17 = 1) by the pull-up resistor setting register (RDR1). (When the power output is set, it is invalid.) General purpose input/output port. General purpose input/output port. Functions as output pins of PPG timers ch0. General purpose input/output port.
33 to 40 41 to 44 45
P10 to P17 P20 to P23 P24 PPG0 P25 to P27 PPG1 to PPG3 P40 TIN0 P41 TOT0 P42 SIN0 P43 SOT0 P44 SCK0 P45 SIN1 P46 SOT1 P47 SCK1 P50 P51 P52, P53 P54
I D D
51 to 53
D
Functions as output pins of PPG timers ch1 to ch3. General purpose input/output port. Function as event input pin of 16-bit reload timer. General purpose input/output port. Port input Function as output pin of 16-bit reload timer. (High-Z) General purpose input/output port. Functions as a data input pin for UART ch0. General purpose input/output port. Functions as a data output pin for UART ch0. General purpose input/output port. Functions as a clock I/O pin for UART ch0. General purpose input/output port. Functions as a data input pin for UART ch1. General purpose input/output port. Functions as a data output pin for UART ch1. General purpose input/output port. Functions as a clock I/O pin for UART ch1. General purpose input/output port. General purpose input/output port. General purpose input/output port. General purpose input/output port.
62 63 11 12 13 14 15 16 50 64 17, 18 24
H H H H H H H H K K K K
* : For circuit information, see "s I/O CIRCUIT TYPE".
(Continued)
6
MB90335 Series
(Continued) Pin no.
QFPM09 54, 55 Pin name P60, P61 INT0, INT1 P62 56 INT2 SIN P63 57 INT3 SOT P64 58 INT4 SCK P65 59 INT5 PWC P66 INT6 60 SCL0 P67 61 INT7 SDA0 1 3 4 7 8 10 21, 22 20 5 9 49 2 6 19 48 VBUS DVM DVP HVM HVP HCONX MD1, MD0 MD2 Vcc Vcc Vcc Vss Vss Vss Vss C J J J J E B G Power supply C C C C Port input (High-Z) C C
Circuit type* C
Status at reset/ function
Function General purpose input/output port. (withstand voltage of 5 V) Functions as the input pin for external interrupt ch0 and ch1. General purpose input/output port. (withstand voltage of 5 V) Functions as the input pin for external interrupt ch2. Data input pin for simple serial IO. General purpose input/output port. (withstand voltage of 5 V) Functions as the input pin for external interrupt ch3. Data output pin for simple serial IO General purpose input/output port. (withstand voltage of 5 V) Functions as the input pin for external interrupt ch4. Clock I/O pin for simple serial IO. General purpose input/output port. (withstand voltage of 5 V) Functions as the input pin for external interrupt ch5. Functions as the PWC input pin. General purpose input/output port. Functions as the input pin for external interrupt ch6. Functions as the input/output pin for I2C interface clock. The port output must be placed in High-Z state during I2C interface operation. General purpose input/output port. Functions as the input pin for external interrupt ch7. Functions as the I2C interface data input/output pin. The port output must be placed in High-Z state during I2C interface operation.
VBUS input Status detection pin of USB cable. USB function D - pin. USB input USB function D + pin. (SUSPEND) USB Mini Host D - pin. USB Mini Host D + pin. High output External pull-up resistor connection pin. Mode input Input pin for selecting operation mode. Pin Power supply pin. Power supply pin. Power supply pin. Power supply pin (GND). Power supply pin (GND). Power supply pin (GND). Power supply pin (GND).
* : For circuit information, see "s I/O CIRCUIT TYPE". 7
MB90335 Series
s I/O CIRCUIT TYPE
Type
X1
Circuit Clock input
Remarks * Oscillation feedback resistance : approx. 1 M * With standby control
A
X0
Standby control signal * CMOS hysteresis input B Hysteresis input * Hysteresis input * Nch open drain output
Nch Nout
C Hysteresis input Standby control signal * CMOS output * CMOS hysteresis input (With input interception function at standby) Note : * The I/O ports and internal resources share one output buffer for their outputs. * The I/O port and internal resources share one input buffer for their input. * CMOS output
Pch Pout
Pch
Pout
Nch
Nout
D Hysteresis input Standby control signal
E
Nch Nout
* CMOS hysteresis input with pull-up * Resistor approx. 50 k F Hysteresis input
G
Hysteresis input
* CMOS hysteresis input with pull-down * Resistor approx. 50 k * FLASH product is not provided with pull-down resistor.
(Continued)
8
MB90335 Series
(Continued) Type
Pch
Circuit Open drain control signal
Remarks * CMOS output * CMOS hysteresis input (With input interception function at standby) With open drain control signal
Pout
H
Nch
Nout
Hysteresis input Standby control signal
CTL Pch Pout
I
Nch
Nout
* CMOS output * CMOS input (With input interception function at standby) Programmable pull-up Resistor approx. 50 k
CMOS input Standby control signal * USB I/O pin D + input
D+ D-
D-input Differential input Full D + output
J
Full D-output Low D + output Low D-output Direction Speed * CMOS output * CMOS input (With input interception function at standby)
Pch
Pout
K
Nch
Nout
CMOS input Standby control signal
9
MB90335 Series
s HANDLING DEVICES
1. Preventing latchup and turning on power supply
Latchup may occur on CMOS IC under the following conditions: 1. If a voltage higher than VCC or lower than VSS is applied to input and output pins. 2. A voltage higher than the rated voltage is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using CMOSICs, take great care to prevent the occurrence of latchup.
2. Treatment of unused pins
Leaving unused input pins open may cause a malfunction. These pins must therefore be set to a pull-up or pulldown state.
3. About the attention when the external clock is used
* Using external clock
X0
OPEN
X1
4. Treatment of power supply pins (VCC/VSS)
When the device is provided with multiple VCC and VSS pins, be sure to connect all of the power pins to the power supply and ground outside the device to reduce latch-up and unwanted radiation, prevent the strobe signal from malfunctioning due to a rise of grand level, and to follow the standards of total output current for device design reasons. The power supply source should be connected to the VCC and VSS of this device at the lowest possible impedance. It is also advisable to connect a bypass capacitor of approximately 0.1 F between VCC and VSS near this device.
5. About crystal oscillator circuit
Noise near the X0/X1 pin may cause the device to malfunction. When designing the artwork for a PC board using the microcontroller, it is strongly advisable to place the X0/X1 and crystal (ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible and prevent their writing patterns from crossing other patterns as possible be cause stable operation can be expected with such a layout.
6. Caution on Operations during PLL Clock Mode
Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL internal automatic oscillator circuit.Performance of this operation, however, cannot be guaranteed.
10
MB90335 Series
7. Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. For stabilization reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values) at commercial frequencies (50 MHz to 60 MHz) fall below 10% of the standard VCC supply voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching.
8. Writing to flash memory
For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V.
11
MB90335 Series
s BLOCK DIAGRAM
X0, X1 RST MD0 to MD2
Clock control circuit Interrupt controller
RAM ROM
F2MC-16LX CPU
8/16-bit PPG timer ch0 to ch3* 16-bit PWC
PPG0 to PPG3
SIN0, SIN1 SOT0, SOT1 SCK0, SCK1 SCL0 SDA0
PWC SIN SOT SCK
UART/SIO ch0, ch1 I2C
Internal data bus
SIO DMAC
TOT0 TIN0 DVP DVM HVP HVM HCONX VBUS INT0 to INT7
16-bit reload timer
USB (Function) (Mini-HOST)
External interrupt
I/O port (port 0, 1, 2, 4, 5, 6)
P00 P07
P10 P17
P20 P27
P40 P47
P50 P54
P60 P67
* : Channel for use in 8-bit mode. Two channels (ch1, ch3) are used in 16-bit mode. Note : I/O ports share pins with peripheral resources. For details, see "s PIN ASSIGNMENT" and "s PIN DESCRIPTION". Note also that pins used for peripheral resources cannot serve as I/O ports.
12
MB90335 Series
s MEMORY MAP
Single chip mode (ROM mirror function)
MB90V330A
FFFFFFH FF0000H
MB90F337
FFFFFFH FF0000H
MB90337
FFFFFFH FF0000H
ROM (FF bank)
ROM (FF bank)
ROM (FF bank)
00FFFFH 008000H 007FFFH 007900H 007100H
ROM area (image of FF bank)
00FFFFH 008000H 007FFFH 007900H
ROM area (image of FF bank)
00FFFFH 008000H 007FFFH 007900H
ROM area (image of FF bank)
Peripheral area
Peripheral area
Peripheral area
RAM area (28 Kbytes)
000100H 0000FBH
001100H
RAM area (4 Kbytes)
001100H
RAM area (4 Kbytes)
Register
000100H 0000FBH
Register
000100H 0000FBH
Register
Peripheral area
000000H 000000H
Peripheral area
000000H
Peripheral area
Memory Map of MB90335 Series Notes : * When the ROM mirror function register has been set, the mirror image data at higher addresses ("FF8000H to FFFFFFH" ) of bank FF is visible from the higher addresses ("008000H to 00FFFFH") of bank 00. * For setting the ROM mirror function, see "16. ROM mirror function select module" in "s PERIPHERAL RESOURCES". Reference : * The ROM mirror function is for using the C compiler small model. * The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. * When the C compiler small model is used, the data table mirror image can be shown at "008000H to 00FFFFH" by storing the data table at "FF8000H to FFFFFFH". Therefore, data tables in the ROM area can be referenced without declaring the far addressing with the pointer.
13
MB90335 Series
s F2MC-16L CPU PROGRAMMING MODEL
* Dedicated register
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bit 16 bit 32 bit
Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General purpose registers
MSB 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16 bit LSB
* Processor status
15 PS ILM 13 12 RP 87 CCR 0
14
MB90335 Series
s I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H to 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H SMR0 SCR0 SIDR0 SODR0 SSR0 UTRLR0 UTCR0 SMR1 SCR1 SIDR1 SODR1 SSR1 Serial Mode Register ch0 Serial Control Register ch0 Serial Input Data Register ch0 Serial Output Data Register ch0 Serial Status Register ch0 UART Prescaler Reload Register ch0 UART Prescaler Control Register ch0 Serial Mode Register ch1 Serial Control Register ch1 Serial Input Data Register ch1 Serial Output Data Register ch1 Serial Status Register ch1 ODR4 RDR0 RDR1 Port 4 Output Pin Register Port 0 Pull-up Resistance Register Port 0 Pull-up Resistance Register Prohibited R/W R/W R W R/W R/W R/W R/W R/W R W R/W UART1 UART0 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 0 0 0B Communication 0 0 0 0 0 0 0 0B Prescaler (UART0) 0 0 0 0 - 0 0 0B 0 0 1 0 0 0 0 0B 0 0 0 0 0 1 0 0B XXXXXXXXB 0 0 0 0 1 0 0 0B DDR4 DDR5 DDR6 Port 4 Direction Register Port 5 Direction Register Port 6 Direction Register Prohibited R/W R/W R/W Port 4 (OD control) 0 0 0 0 0 0 0 0B DDR0 DDR1 DDR2 Port 0 Direction Register Port 1 Direction Register Port 2 Direction Register Prohibited R/W R/W R/W Port 4 Port 5 Port 6 0 0 0 0 0 0 0 0B - - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B PDR4 PDR5 PDR6 Port 4 Data Register Port 5 Data Register Port 6 Data Register Prohibited R/W R/W R/W Port 0 Port 1 Port 2 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B Register abbreviation PDR0 PDR1 PDR2 Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Prohibited R/W R/W R/W Port 4 Port 5 Port 6 XXXXXXXXB - - - XXXXXB XXXXXXXXB Read/ Write R/W R/W R/W Resource name Port 0 Port 1 Port 2 Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB
Port 0 (PULL-UP) 0 0 0 0 0 0 0 0B Port 1 (PULL-UP) 0 0 0 0 0 0 0 0B
(Continued)
15
MB90335 Series
Address 00002AH 00002BH 00002CH to 00003BH 00003CH 00003DH 00003EH 00003FH 000040H to 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH to 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H
Register abbreviation UTRLR1 UTCR1
Register UART Prescaler Reload Register ch1 UART Prescaler Control Register ch1 Prohibited
Read/ Write R/W R/W
Resource name
Initial Value
Communication 0 0 0 0 0 0 0 0B Prescaler (UART1) 0 0 0 0 - 0 0 0B
ENIR EIRR ELVR
Interrupt/DTP Enable Register Interrupt/DTP source Register Request Level Setting Register Lower Request Level Setting Register Higher Prohibited
R/W R/W R/W R/W DTP/External interrupt
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
PPGC0 PPGC1 PPGC2 PPGC3
PPG0 Operation Mode Control Register PPG1 Operation Mode Control Register PPG2 Operation Mode Control Register PPG3 Operation Mode Control Register Prohibited
R/W R/W R/W R/W
PPG ch0 PPG ch1 PPG ch2 PPG ch3
0X0 0 0XX1B 0X0 0 0 0 0 1B 0X0 0 0XX1B 0X0 0 0 0 0 1B
PPG01 PPG23
PPG0 and PPG1 Output Control Register Prohibited PPG2 and PPG3 Output Control Register Prohibited
R/W R/W
PPG ch0/1 PPG ch2/3
0 0 0 0 0 0XXB 0 0 0 0 0 0 XXB
SMCS SDR SDCR PWCSR PWCR DIVR
Serial Mode Control Status Register Serial Data Register Communication Prescaler Control Register PWC Control Status Register PWC Data Buffer Register PWC Dividing Ratio Register Prohibited
R/W R/W R/W R/W R/W R/W
Extended Serial I/O Communication Prescaler
XXXX0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB 0XXX0 0 0 0B 0 0 0 0 0 0 0 0B
16-bit PWC Timer
0 0 0 0 0 0 0 XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - 0 0B 0 0 0 0 0 0 0 0B XXXX 0 0 0 0B
TMCSR0 TMR0 TMRLR0 TMR0 TMRLR0
Timer control status Register 16-bit Timer Register Lower 16-bit Reload Register Lower 16-bit Timer Register Higher 16-bit Reload Register Higher
R/W R W R W 16-bit Reload Timer
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
16
MB90335 Series
Address 000066H to 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H to 00009AH 00009BH 00009CH 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H 0000A3H 0000A4H 0000A5H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH
Register abbreviation
Register Prohibited ROM Mirroring Function Selection Register I2C Bus Status Register I C Bus Control Register I C Bus Clock Selection Register I C Bus Address Register I C Bus Data Register Prohibited
2 2 2 2
Read/ Resource name Write
Initial Value
ROMM IBSR0 IBCR0 ICCR0 IADR0 IDAR0
W R R/W R/W R/W R/W
ROM Mirror Function Selection Module
- - - - - - 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
I C Bus Interface XX 0 XXXXXB XXXXXXXXB XXXXXXXXB
2
DCSR DSRL DSRH PACSR DIRR LPMCR CKSCR
DMA Descriptor Channel Specification Register DMA Status Register Lower DMA Status Register Higher Program Address Detection Control Status Register Delayed Interrupt Source generate/ release Register Low Power Consumption Mode Register Clock Selection Register Prohibited
R/W R/W R/W R/W R/W R/W R/W Address Match Detection Delayed Interrupt Low Power Consumption control circuit Clock DMAC
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
DSSR
DMA Stop Status Register Prohibited
R/W
DMAC
0 0 0 0 0 0 0 0B
WDTC TBTC
Watchdog Control Register Time-base Timer Control Register Prohibited
R/W R/W
Watchdog Timer X - XXX 1 1 1B Time-base Timer 1 - - 0 0 1 0 0B
DERL DERH FMCR
DMA Enable Register Lower DMA Enable Register Higher Flash Memory Control Status Register Prohibited
R/W R/W R/W
DMAC FLASH MEMORY I/F
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 X 0 0 0 0B
(Continued)
17
MB90335 Series
Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H
Register abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 HCNT0 HCNT1 HIRQ HERR HSTATE HFCOMP
Register Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15 USB Host Control Register 0 USB Host Control Register 1 USB Host Interruption Register USB Host Error Status Register USB Host State Status Register USB SOF Interrupt FRAME compare Register USB Retry Timer Setting Register 0 USB Retry Timer Setting Register 1 USB Retry Timer Setting Register 2 USB Host Address Register USB EOF Setting Register 0 USB EOF Setting Register 1 USB FRAME Setting Register 0 USB FRAME Setting Register 1 USB Host Token End Point Register Prohibited UDC Control Register Prohibited
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Interrupt Controller
0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B XX 0 1 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
HRTIMER HADR HEOF HFRAME HTOKEN UDCC
USB Mini HOST
0 0 0 0 0 0 0 0B XXXXXX 0 0B X 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX 0 0 0B 0 0 0 0 0 0 0 0B
USB function
1 0 1 0 0 0 0 0B
(Continued)
18
MB90335 Series
Address 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H 0000F6H 0000F7H 0000F8H 0000F9H
Register abbreviation EP0C EP1C EP2C EP3C EP4C EP5C TMSP UDCS UDCIE EP0IS EP0OS EP1S EP2S EP3S EP4S EP5S EP0DT EP1DT EP2DT EP3DT EP4DT
Register EP0 Control Register EP1 Control Register EP2 Control Register EP3 Control Register EP4 Control Register EP5 Control Register Time Stamp Register UDC Status Register Interrupt Enable Register EP0I Status Register EP0O Status Register EP1 Status Register EP2 Status Register EP3 Status Register EP4 Status Register EP5 Status Register EP0 Data Register EP1 Data Register EP2 Data Register EP3 Data Register EP4 Data Register
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value X 1 0 0 0 0 0 0B XXXX 0 0 0 XB 0 0 0 0 0 0 0 0B 0 1 1 0 0 0 0 1B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 1 0 XXX 1 XXB XXXXXXXXB 1 0 0 XX 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
USB Function
(Continued)
19
MB90335 Series
Address 0000FAH 0000FBH 0000FCH to 0000FFH 000100H to 001100H 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 007900H 007901H 007902H 007903H 007904H 007905H 007906H 007907H 007908H to 00790BH 00790CH 00790DH 00790EH 00790FH to 00791FH
Register abbreviation EP5DT
Register EP5 Data Register
Read/ Write R/W R/W Prohibited
Resource name USB Function
Initial Value XXXXXXXXB XXXXXXXXB
RAM Area Program Address Detection Register ch0 Lower PADR0 Program Address Detection Register ch0 Middle Program Address Detection Register ch0 Higher Program Address Detection Register ch1 Lower PADR1 Program Address Detection Register ch1 Middle Program Address Detection Register ch1 Higher PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PPG Reload Register Lower ch0 PPG Reload Register Higher ch0 PPG Reload Register Lower ch1 PPG Reload Register Higher ch1 PPG Reload Register Lower ch2 PPG Reload Register Higher ch2 PPG Reload Register Lower ch3 PPG Reload Register Higher ch3 Prohibited FWR0 FWR1 SSR0 Flash Program Control Register 0 Flash Program Control Register 1 Sector Conversion Setting Register Prohibited R/W R/W R/W Flash Flash Flash 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 XXXXX0B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PPG ch0 PPG ch1 PPG ch2 PPG ch3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address Match Detection
(Continued)
20
MB90335 Series
(Continued)
Address 007920H 007921H 007922H 007923H 007924H 007925H 007926H 007927H 007928H to 007FFFH * Explanation on read/write R/W Read and write enabled R Read only W Write only * Explanation of initial values 0 : Initial Value is "0". 1 : Initial Value is "1". X : Initial Value is undefined. : Initial Value is undefined (None). Note : No IO instruction can be used for registers located between 007900H to 007FFFH. Register abbreviation DBAPL DBAPM DBAPH DMACS DIOAL DIOAH DDCTL DDCTH Register DMA Buffer Address Pointer Lower 8-bit DMA Buffer Address Pointer Middle 8-bit DMA Buffer Address Pointer Higher 8-bit DMA Control Register DMA I/O Register Address Pointer Lower 8-bit DMA I/O Register Address Pointer Higher 8-bit DMA Data Counter Lower 8-bit DMA Data Counter Higher 8-bit Prohibited Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W DMAC Resource name Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
21
MB90335 Series
s INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT 9 instruction Exceptional treatment USB Function1 USB Function2 USB Function3 USB Function4 USB Mini-HOST1 USB Mini-HOST2 I2C ch0 DTP/External interrupt ch0/1 No DTP/External interrupt ch2/3 No DTP/External interrupt ch4/5 PWC/Reload timer ch0 DTP/External interrupt ch6/7 No No No No No PPG ch0/1 No PPG ch2/3 No No No No UART (Send completed) ch0/ch1 Extended serial I/O UART(Reception completed) ch0/ch1 Time-base timer Flash memory status Delayed interrupt output module 22 x x x x x x EI2OS DMAC support x x x x x x x x x x x x x 0, 1 2 to 6 x x x x x x x x 14 x x x 13 9 12 x x x Interrupt vector Number* #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH Interrupt control Prioriregister ty Address ICR Address High
FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH
Low
MB90335 Series
: Available. EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. There is a stop demand.) : Available (The interrupt request flag is cleared by the interrupt clear signal). : Available when any interrupt source sharing ICR is not used. x : Unavailable * If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS. * The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR). Note : If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the DMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the appropriate resource, and take measures by software polling.
s USB INTERRUPT FACTOR CONTENTS
USB interrupt factor USB function 1 USB function 2 USB function 3 USB function 4 USB Mini-HOST1 USB Mini-HOST2 End Point 1-5 VOFF, VON, SUSP, SOF, BRST, WKOP, COHF SPIT DIRQ, CHHIRQ, URIRQ, RWKIRQ SOFIRQ, CMPIRQ Details End Point0-IN, EndPoint 0-OUT
23
MB90335 Series
s PERIPHERAL RESOURCES
1. I/O port
* The I/O ports are used as general-purpose input/output ports (parallel I/O ports). MB90335 series model is provided with 6 ports (45 inputs) . The ports function as input/output pins for peripheral functions also. * An I/O port, using port data register (PDR) , outputs the output data to I/O pin and input a signal input to I/O port. The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis. * The following table lists the I/O ports and the peripheral functions with which they share pins. Port pin name Pin Name (Peripheral) Peripheral Function that Shares Pin Port 0 Port 1 Port 2 P00 to P07 P10 to P17 P20 to P23 P24 to P27 P40, P41 Port 4 Port 5 P42 to P47 P50 to P54 P60, P61 Port 6 P62 to P64 P65 P66, P67 PPG0 to PPG3 TIN0, TOT0 SIN0, SOT0, SCK0, SIN1, SOT1, SCK1 INT0, INT1 INT2 to INT4, SIN, SOT, SCK INT5, PWC External interrupt External interrupt, serial IO External interrupt, PWC 8/16 bit PPG timer 0, 1 16-bit reload timer UART0, 1
INT6, INT7, SCL0, SDA0 External interrupt, I2C
24
MB90335 Series
* Register list (port data register) PDR0 Address : 000000H PDR1 Address : 000001H PDR2 Address : 000002H PDR4 Address : 000004H PDR5 Address : 000005H PDR6 Address : 000006H
7 P07 15 P17 7 P27 7 P47 15 7 P67 6 P06 14 P16 6 P26 6 P46 14 6 P66 5 P05 13 P15 5 P25 5 P45 13 5 P65 4 P04 12 P14 4 P24 4 P44 12 P54 4 P64 3 P03 11 P13 3 P23 3 P43 11 P53 3 P63 2 P02 10 P12 2 P22 2 P42 10 P52 2 P62 1 P01 9 P11 1 P21 1 P41 9 P51 1 P61 0 P00 8 P10 0 P20 0 P40 8 P50 0 P60
Initial Value XXXXXXXXB
Access R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
XXXXXXXXB
R/W*
- - - XXXXXB
R/W*
XXXXXXXXB
R/W*
* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows: * Input mode Read : The level at the relevant pin is read. Write : Data is written to the output latch. * Output mode Read : The data register latch value is read. Write : Data is output to the relevant pin.
25
MB90335 Series
* Register list (port direction register) DDR0 Address : 000010H DDR1 Address : 000011H DDR2 Address : 000012H DDR4 Address : 000014H DDR5 Address : 000015H DDR6 Address : 000016H *
7 D07 15 D17 7 D27 7 D47 15 7 D67 6 D06 14 D16 6 D26 6 D46 14 6 D66 5 D05 13 D15 5 D25 5 D45 13 5 D65 4 D04 12 D14 4 D24 4 D44 12 D54 4 D64 3 D03 11 D13 3 D23 3 D43 11 D53 3 D63 2 D02 10 D12 2 D22 2 D42 10 D52 2 D62 1 D01 9 D11 1 D21 1 D41 9 D51 1 D61 0 D 00 8 D10 0 D20 0 D40 8 D50 0 D60
Initial Value Access 00000000B R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
- - - 00000B
R/W
00000000B
R/W
When each pin is serving as a port, the corresponding pin is controlled as follows: 0 : Input mode 1 : Output mode This bit becomes 0 after a reset.
Note : If these registers are accessed by a read modify write instruction (such as a bit set instruction) , the bits manipulated by the instruction are set to prescribed values but those other bits in output registers which have been set for input are rewritten to the current input values of the pins. When switching a pin from input port to output port, therefore, write a desired value in the PDR first, then set the DDR to switch the pin for output. * Register list (Port pull-up register) RDR0 Address : 00001CH RDR1 Address : 00001DH
7 RD07 15 RD17 6 RD06 14 RD16 5 RD05 13 RD15 4 RD04 12 RD14 3 RD03 11 RD13 2 RD02 10 RD12 1 RD01 9 RD11 0 RD00 8 RD10
Initial Value Access 00000000B R/W
00000000B
R/W
Controls the pull-up resistor in input mode. 0 : Without pull-up resistor in input mode. 1 : With Pull-up resistor in input mode. Meaningless in output mode (without pull-up resistor) ./ The input/output register is decided by the setting of the direction register (DDR) . No pull-up resistor is used in stop mode (SPL = 1).
26
MB90335 Series
* Register list (output pin register) ODR4 Address : 00001BH
7 OD47 6 OD46 5 OD45 4 OD44 3 OD43 2 OD42 1 OD41 0 OD40
Initial Value Access 00000000B R/W
Controls open-drain output in output mode. 0 : Serves as a standard output port in output mode. 1 : Serves as an open-drain output port in output mode. Meaningless in input mode. (output High-Z) / The input/output register is decided by the setting of the direction register (DDR) . * Block diagram of port 0 pin and port1 pin
Pull-up resistor setting register (RDRx)
Internal data bus
Built-in pull-up resistor
PDRx read
Port data register (PDRx) Port direction register (DDRx)
I/O decision circuit
Input buffer Output buffer Port pin
PDRx Write
Standby control (LPMCR : SPL = "1")
* Block diagram of port 2 pin, port 4 pin, port 5 pin and port 6 pin
Resource input Internal data bus
PDRx read
Port data register (PDRx) Port direction register (DDRx)
I/O decision circuit
input buffer Output buffer Port pin
PDRx write
Standby control (LPMCR : SPL = "1")
Resource output control signal Release output
27
MB90335 Series
2. Time-base timer
* The time-base timer is an 18-bit free-running counter (time-base timer counter) that counts in synchronization with the main clock (2 cycles of the oscillation clock HCLK). * Four different time intervals can be selected, for each of which an interrupt request can be generated. * Operating clock signals are supplied to peripheral resources such as the oscillation stabilization wait timer and watchdog timer. * Interval time of time-base timer Internal count clock cycle 212/HCLK (Approx. 0.68 ms) 2/HCLK (0.33 s) 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Notes : * HCLK : Oscillation clock frequency * The parenthesized values assume an oscillator clock frequency of 6 MHz. * Clock cycles supplied from time-base timer Where to supply clock 2 /HCLK (Approx. 1.36 ms) Oscillation stabilization wait of main clock 215/HCLK (Approx. 5.46 ms) 217/HCLK (Approx. 21.84 ms) 212/HCLK (Approx. 0.68 ms) Watch dog timer 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) Notes : * HCLK : Oscillation clock frequency * The parenthesized values assume an oscillator clock frequency of 6 MHz. * Register list Time-base timer control register (TBTC)
15 14 () 13 () 12 TBIE ( R/W ) 11 TBOF ( R/W ) 10 TBR (W) 9 TBC1 ( R/W ) 8 TBC0 ( R/W )
13
Interval time
Clock cycle
Address : 0000A9H
RESV ( R/W )
Initial Value 1--00100B
Note : For the conditions for clearing the time-base timer, refer to the chapter for the time-base timer in the hardware manual.
28
MB90335 Series
* Block Diagram
To watchdog timer
To PPG timer Time-base timer counter
Dividing HCLK by 2
x 21 x 22 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF OF OF
Power-on reset Stop mode start
Counter clear control circuit
To clock controller oscillation stabilizing wait time selector Interval timer selector
CKSCR : MCS = 10*1
TBOF set TBOF clear
Time-base timer control register (TBTC) RESV Time-base timer interrupt signal
TBIE TBOF TBR TBC1 TBC0
OF HCLK *1
:Unused :Overflow :Oscillation clock :Switching the machine clock from main clock to PLL clock
Actual interrupt request number of time-base timer is as follows: Interrupt request number:#40 (28H)
29
MB90335 Series
3. Watchdog timer
* The watchdog timer is a timer counter prepared in case programs run out of control. * The watchdog timer is a 2-bit counter using the time-base timer as the count clock. * When started, the watchdog timer resets the CPU if it is not cleared before the two-bit counter overflows. * Interval time of watchdog timer HCLK: Oscillation clock (6 MHz) Min Approx. 2.39 ms Approx. 9.56 ms Approx. 38.23 ms Approx. 305.83 ms Max Approx. 3.07 ms Approx. 12.29 ms Approx. 49.15 ms Approx. 393.22 ms Clock cycle 2 211 / HCLK
14
216 213 / HCLK 218 215 / HCLK 221 218 / HCLK
Notes : * The maximum and minimum time intervals for the watchdog timer depend on the counter clear timing. * The watchdog timer contains a 2-bit counter that counts the carry signals of the time-base timer. When the device is operating with HCLK, therefore, clearing the time-base timer lengthens the watchdog reset generation time interval. * Event that stop the watchdog timer 1 : Stop due to a Power-on reset 2 : watchdog reset * Clear factor of watch dog timer 1 : External reset input by RST pin 2 : Writing "0" to the software reset bit 3 : Writing "0" to the watchdog control bit (second and subsequent times) 4 : Transition to sleep mode (Clearing the watchdog timer, and suspend counting) 5 : Transition to time-base timer mode (Clearing the watchdog timer, and suspend counting) 6 : Transition to stop mode (Clearing the watchdog timer, and suspend counting) * Register list Watchdog timer control register (WDTC)
7 6 () 5 WRST (R) 4 ERST (R) 3 SRST (R) 2 WTE (W) 1 WT1 (W) 0 WT0 (W)
Address : 0000A8H
PONR (R)
Initial Value X-XXX111B
30
MB90335 Series
* Block Diagram
Watchdog timer control register (WDTC)
PONR WRST ERST SRST WTE WT1 WT0
2
Timer-base timer mode start Sleep mode start
Watchdog timer
Counter clear control circuit Count clock selector
CLR
CLR and start 2-bit counter
CLR
Stop mode start
watchdog timer reset generation circuit
To internal reset generation circuit
Clear
Dividing HCLK by 2
x 21 x 22
4
Time-base timer counter
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
HCLK: Oscillation clock
31
MB90335 Series
4. 16 - bit Reload Timer
The 16-bit reload timer has the internal clock mode to be decrement in synchronization with three different internal clocks and the event count mode to decrement upon detection of an arbitrary edge of the pulse input to the external pin. Either can be selected. This timer defines when the count value changes from 0000H to FFFFH as an underflow. The timer therefore causes an underflow when the count reaches [reload register setting +1]. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. * Register list * Timer control status register Timer control status register (Higher) (TMCSR0)
15 14 () 13 () 12 () 11 CSL1 ( R/W ) 10 CSL0 ( R/W ) 9 MOD2 ( R/W ) 8 MOD1 ( R/W )
Address : 000063H
()
Initial Value XXXX0000B
Timer control status register (Lower) (TMCSR0)
7 6 OUTE ( R/W ) 5 OUTL ( R/W ) 4 RELD ( R/W ) 3 INTE ( R/W ) 2 UF ( R/W ) 1 CNTE ( R/W ) 0 TRG ( R/W )
Address : 000062H
MOD0 ( R/W )
Initial Value 00000000B
* 16-bit timer register/16-bit reload register TMR0/TMRLR0 (Higher)
15 14 D14 ( R/W ) 13 D13 ( R/W ) 12 D12 ( R/W ) 11 D11 ( R/W ) 10 D10 ( R/W ) 9 D09 ( R/W ) 8 D08 ( R/W )
Address : 000065H
D15 ( R/W )
Initial Value XXXXXXXXB
TMR0/TMRLR0 (Lower)
7 6 D06 ( R/W ) 5 D05 ( R/W ) 4 D04 ( R/W ) 3 D03 ( R/W ) 2 D02 ( R/W ) 1 D01 ( R/W ) 0 D00 ( R/W )
Address : 000064H
D07 ( R/W )
Initial Value XXXXXXXXB
32
MB90335 Series
* Block Diagram Internal data bus
TMRLR0
16-bit reload register
Reload signal Reload control circuit
TMR0
2
16-bit timer register
CLK
UF
Count clock generation circuit
Machine clock
Prescaler
3
Gate input
Valid clock decision circuit
Wait signal
Clear Trriger Input control circuit
Internal clock
CLK
Output control circuit
Output signal generation circuit
Pin
TIN0
Clock selector External clock
Pin
EN TOT0
3
2
Select signal
Select function
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
Operating Control circuit
UF CNTE TRG
Timer control status register (TMCSR0)
*1 : Interrupt number *2 : Underflow
Interrupt request output #23 (17H)*1
33
MB90335 Series
5. Multifunction timer
* The multifunction timer can be used for waveform output, input pulse width measurement, and external clock cycle measurement. * Configuration of a multi-functional timer 8/16 bit PPG timer 8 bit x 4 ch (16 bit x 2 ch) * 8/16 bit PPG timer (8 bit : 4 channels, 16 bit : 2 channels) 8/16 bit PPG timer consists of a 8 bit down counter (PCNT) , PPG control register (PPGC0 to PPGC3) , PPG clock control register (PCS01, PCS23) and PPG reload register (PRLL0 to PRLL3, PRLH0 to PRLH3) . When used as an 8/16 bit reload timer, the PPG timer serves as an event timer. It can also output pulses of an arbitrary duty ratio at an arbitrary frequency. * 8 bit PPG mode Each channel operates as an independent 8 bit PPG. * 8 bit prescaler + 8 bit PPG mode Operates as an arbitrary-cycle 8 bit PPG with ch0 (ch2) operating as an 8 bit prescaler and ch2 (ch3) counted by the borrow output of ch0 (ch2). * 16 bit PPG mode Operates as a 16 bit PPG with ch0 (ch2) and ch1 (ch3) connected. * PPG Operation The PPG timer outputs pulses of an arbitrary duty ratio (the ratio between the High and Low level periods of pulse waveform) at an arbitrary frequency. Can also be used as a D/A converter by an external circuit.
16 bit PWC timer 1 ch
34
MB90335 Series
* Register list PPG operation mode control register (PPGC1/PPGC3) 000047H Address : 000049H (PPGC0/PPGC2) 000046H Address : 000048H
7 PEN0 ( R/W ) 6 () 5 PE0O ( R/W ) 4 PIE0 ( R/W ) 3 PUF0 ( R/W ) 2 () 1 () 0
Reserved
15 PEN1 ( R/W )
14 ()
13 PE10 ( R/W )
12 PIE1 ( R/W )
11 PUF1 ( R/W )
10 MD1 ( R/W )
9 MD0 ( R/W )
8
Reserved
Initial Value 0X000001B
( R/W )
Initial Value 0X000XX1B
( R/W )
PPG output control register (PPG01/PPG23) 00004CH Address : 00004EH PPG reload register (PRLH0 to PRLH3) 007901H 007903H Address : 007905H 007907H (PRLL0 to PRLL3) 007900H 007902H Address : 007904H 007906H
7 PCS2 ( R/W ) 6 PCS1 ( R/W ) 5 PCS0 ( R/W ) 4 PCM2 ( R/W ) 3 PCM1 ( R/W ) 2 1 0 PCM0 Reserved Reserved ( R/W ) ( R/W ) ( R/W )
Initial Value 000000XXB
15 D15 ( R/W )
14 D14
13 D13
12 D12 ( R/W )
11 D11 ( R/W )
10 D10
9 D09
8 D08 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
( R/W ) ( R/W )
7 D07 ( R/W )
6 D06
5 D05
4 D04 ( R/W )
3 D03 ( R/W )
2 D02
1 D01
0 D00 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
( R/W ) ( R/W )
35
MB90335 Series
* 8 bit PPG ch0/2 block diagram
Peripheral clock x 16 PPG 0/2 output enable Peripheral clock x 8 Peripheral clock x 4 Peripheral clock x 2 Peripheral clock PPG 0/2 output latch
PPG0/2 A/D converter
PEN0 PCNT (down counter) Count clock selector
S RQ
To interrupt IRQ #30 (1EH)* #32 (20H)*
ch1/3/5 borrow L/H selector
Timebase counter output main clock x 512
PUF0
PIE0
L/H selector
PRLL PRLHB PPGC0 (operation mode control) PRLL L data bus H data bus
* : Interrupt number
36
MB90335 Series
* 8 bit PPG ch1/3 block diagram
Peripheral clock x 16 PPG 1/3 output enable Peripheral clock x 8 Peripheral clock x 4 Peripheral clock x 2 Peripheral clock PPG 1/3 output latch
PPG1/3
PEN1 PCNT0 (down counter) Count clock selector
S R
Q
To interrupt IRQ #30 (1EH)* #32 (20H)*
L/H selector
Timebase counter output main clock x 512
PUF1
PIE1
L/H selector
PRLL PRLHB PPGC0 (operation mode control) PRLL L data bus H data bus
* : Interrupt number
37
MB90335 Series
* PWC timer The PWC timer is a 16 bit multifunction up-count timer capable of measuring the input signal pulse width. * Register list PWC control status register (PWCSR)
15 14 STOP ( R/W ) 13 EDIR (R) 12 EDIE ( R/W ) 11 OVIR ( R/W ) 10 OVIE ( R/W ) 9 ERR (R) 8
Reserved
Address : 00005DH
STRT ( R/W )
Initial Value 0000000XB
( R/W )
7
6 CKS0 ( R/W )
5 PIS1 ( R/W )
4 PIS0 ( R/W )
3 S/C ( R/W )
2 MOD2 ( R/W )
1 MOD1 ( R/W )
0 MOD0 ( R/W )
Address : 00005CH
CKS1 ( R/W )
Initial Value 00000000B
PWC data buffer register (PWCR)
15 14 D14 ( R/W ) 13 D13 ( R/W ) 12 D12 ( R/W ) 11 D11 ( R/W ) 10 D10 ( R/W ) 9 D9 ( R/W ) 8 D8 ( R/W )
Address : 00005FH
D15 ( R/W )
Initial Value 00000000B
7
6 D6 ( R/W )
5 D5 ( R/W )
4 D4 ( R/W )
3 D3 ( R/W )
2 D2 ( R/W )
1 D1 ( R/W )
0 D0 ( R/W )
Address : 00005EH
D7 ( R/W )
Initial Value 00000000B
Ratio of dividing frequency control register (DIVR)
7 6 () 5 () 4 () 3 () 2 () 1 DIV1 ( R/W ) 0 DIV0 ( R/W )
Address : 000060H
()
Initial Value ------00B
38
MB90335 Series
* Block Diagram
PWCR read
Error detection
ERR PWCR 16
Reload Data transfer Overflow F2MC-16 bus
16
Internal clock (Machine clock/4)
16 bit up-count timer
Clock
Timer clear
22 23 CKS1/CKS0
Clock devider
Divider clear
Control circuit
Start edge selection Measurement starting edge Measurement termination edge Measurement termination interrupt request end edge selection
Count enable
Flag set etc...
Control bit output
Edge detection
PIS0/PIS1
Divider ON/OFF
Input waveform comparator
PWC
8-bit divider
Divide ratio select
DIVR
15
Overflow interrupt request
ERR
CKS0/CKS1
PWCSR 2
39
MB90335 Series
6. UART
Overview of UART * UART is a general purpose serial communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. * It supports bi-directional communication (normal mode) and master/slave communication (multi-processor mode: supported on master side only). * An interrupt can be generated upon completion of reception, detection of a reception errror, or upon completion of transmission. EI2OS is supported also. * UART functions UART, or a generic serial data communication interface that sends and receives serial data to and from other CPU and peripherals, has the functions listed in following. Function Data buffer Transmission mode Full-duplex double-buffered * Clock synchronous (without start/stop bit) * Clock asynchronous (start-stop synchronous) * Special-purpose baud-rate generator It is optional from eight kinds. * Baud rate by external clock (clock of SCK0/SCK1 terminal input) * 8 bits or 7 bits (in the asynchronous normal mode only) * 1 to 8 bits (in the synchronous mode only) Non Return to Zero (NRZ) system * Framing error * Overrun error * Parity error (Not supported in operation mode 1) * Receive interrupt (reception completed, reception error detected) * Transmission interrupt (transmission completed) * Both the transmission and reception support EI2OS. Capable of 1 (master) to n (slaves) communication (available just as master)
Baud rate
Data length Signaling system Reception error detection
Interrupt request Master/slave type communication function (multi processor mode)
Note : In clock synchronous transfer mode, the UART transfers only data with no start or stop bit added. UART operation modes Operation mode 0 1 Normal mode Multi processor mode 8 Data length Without parity 8 + 1 *1 With parity 7 bits or 8 bits Synchronization Asynchronous Asynchronous Synchronous Stop bit length 1 bit or 2 bits *2 No
2 Normal mode : Setting disabled
*1 : + 1 is an address/data setting bit (A/D) which is used for communication control. *2 : Only one bit can be detected as a stop bit at reception. 40
MB90335 Series
* Register list Serial mode register (SMR0, SMR1) Address : 000020H 000026H
7 MD1 ( R/W ) 6 MD0 ( R/W ) 5 SCKL ( R/W ) 4 M2L2 ( R/W ) 3 M2L1 ( R/W ) 2 M2L0 ( R/W ) 1 SCKE ( R/W ) 0 SOE ( R/W )
Initial Value 00100000B
Serial control register (SCR0, SCR1) Address : 000021H 000027H
15 PEN ( R/W ) 14 P ( R/W ) 13 SBL ( R/W ) 12 CL ( R/W ) 11 A/D ( R/W ) 10 REC (W) 9 RXE ( R/W ) 8 TXE ( R/W )
Initial Value 00000100B
Serial input/output register (SIDR0, SIDR1 / SODR0, SODR1) Address : 000022H 000028H
7 D7 ( R/W ) 6 D6 ( R/W ) 5 D5 ( R/W ) 4 D4 ( R/W ) 3 D3 ( R/W ) 2 D2 ( R/W ) 1 D1 ( R/W ) 0 D0 ( R/W )
Initial Value XXXXXXXXB
Serial data register (SSR0, SSR1) Address : 000023H 000029H
15 PE (R) 14 ORE (R) 13 FRE (R) 12 RDRF (R) 11 TDRE (R) 10 BDS ( R/W ) 9 RIE ( R/W ) 8 TIE ( R/W )
Initial Value 00001000B
UART prescaler reload register (UTRLR0, UTRLR1) Address : 000024H 00002AH
7 D7 ( R/W ) 6 D6 ( R/W ) 5 D5 ( R/W ) 4 D4 ( R/W ) 3 D3 ( R/W ) 2 D2 ( R/W ) 1 D1 ( R/W ) 0 D0 ( R/W )
Initial Value 00000000B
UART prescaler control register (UTCR0, UTCR1) Address : 000025H 00002BH
15 MD ( R/W ) 14 SRST ( R/W ) 13 CKS ( R/W ) 12
Reserved
11 ()
10 D10 ( R/W )
9 D9 ( R/W )
8 D8 ( R/W )
Initial Value 0000-000B
( R/W )
41
MB90335 Series
Block Diagram
Control bus
Special-purpose baud-rate generator (UART prescaler control register UTCR0, 1)
Reception interrupt signal #39 (27H) Send interrupt signal #37 (25H) Transmission control circuit
Transmission clock
Clock Reception Reception selector control clock
circuit Start bit detection circuit Reception bit counter Reception parity counter
Pin
SCK0, SCK1
Transmission start circuit Transmission bit counter Transmission parity counter
Pin
SOT0, SOT1
Pin
SIN0, SIN1
Shift register for reception
Reception complete
Shift register for transmission
SIDR0, SIDR1
SODR0, SODR1
Receive status decision circuit
Start transmission Reception error occurrence signal for EI2OS (to CPU)
Internal data bus
SMR0, SMR1
MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE
SCR0, SCR1
PEN P SBL CL A/D REC RXE TXE
SSR0, SSR1
PE ORE FRE RDRF TDRE BDS RIE TIE
* : Interrupt number
42
MB90335 Series
7. Extended I/O serial interface
The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit x 1 channel configured clock synchronization scheme. LSB-first or MSB-first transfer mode can be selected for data transfer. There are two serial I/O operation modes available: * Internal shift clock mode: Transfer data in synchronization with the internal clock. * External shift clock mode: Transfer data in synchronization with the clock supplied via the external pin (SCK). By manipulating the general-purpose port sharing the external pin (SCK) in this mode, data can also be transferred by a CPU instruction. * Register list Serial mode control status register (SMCS)
15 14 SMD1 ( R/W ) 6 () 13 SMD0 ( R/W ) 5 () 12 SIE ( R/W ) 4 () 11 SIR ( R/W ) 3 MODE ( R/W ) 10 BUSY ( R/W ) 2 BDS ( R/W ) 9 STOP ( R/W ) 1 SOE ( R/W ) 8 STRT ( R/W ) 0 SCOE ( R/W )
Address :
000059H
SMD2 ( R/W ) 7
Initial Value 00000010 B
Address :
000058H
()
Initial Value XXXX0000 B
Serial data register (SDR)
7 6 D6 ( R/W ) 5 D5 ( R/W ) 4 D4 ( R/W ) 3 D3 ( R/W ) 2 D2 ( R/W ) 1 D1 ( R/W ) 0 D0 ( R/W )
Address :
00005AH
D7 ( R/W )
Initial Value XXXXXXXXB
Communication prescaler control register (SDCR)
15 14 () 13 () 12 () 11 DIV3 ( R/W ) 10 DIV2 ( R/W ) 9 DIV1 ( R/W ) 8 DIV0 ( R/W )
Address : 00005BH
MD ( R/W )
Initial Value 0XXX0000B
43
MB90335 Series
* Block Diagram
Internal data bus
(MSB first) D0 to D7
SIN
D7 to D0 (LSB first) Transfer direction selection
Initial Value
SDR (serial data register)
SOT
Read Write
SCK
Control circuit
Shift clock counter
Internal clock
2
1
0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SMD2 SMD1 SMD0
Interrupt request Internal data bus
44
MB90335 Series
8. I2C Interface
The I2C interface is a serial I/O port supporting the Inter IC BUS. It serves as a master/slave device on the I2C bus and has the following features. * Master/slave sending and receiving * Arbitration function * Clock synchronization function * Slave address and general call address detection function * Detecting transmitting direction function * Start condition repeated generation and detection function * Bus error detection function * Register list I2C bus status register (IBSR0)
7 6 RSC (R) 5 AL (R) 4 LRB (R) 3 TRX (R) 2 AAS (R) 1 GCA (R) 0 FBT (R)
Address : 000070H
BB (R)
Initial Value 00000000B
I2C bus control register (IBCR0)
15 14 BEIE ( R/W ) 13 SCC ( R/W ) 12 MSS ( R/W ) 11 ACK ( R/W ) 10 GCAA ( R/W ) 9 INTE ( R/W ) 8 INT ( R/W )
Address : 000071H
BER ( R/W )
Initial Value 00000000B
I2C bus clock selection register (ICCR0)
7 6 () 5 EN ( R/W ) 4 CS4 ( R/W ) 3 CS3 ( R/W ) 2 CS2 ( R/W ) 1 CS1 ( R/W ) 0 CS0 ( R/W )
Address : 000072H
()
Initial Value XXX0XXXXB
I2C bus address register (IADR0)
15 14 A6 ( R/W ) 13 A5 ( R/W ) 12 A4 ( R/W ) 11 A3 ( R/W ) 10 A2 ( R/W ) 9 A1 ( R/W ) 8 A0 ( R/W )
Address : 000073H
()
Initial Value XXXXXXXXB
I2C bus data register (IDAR0)
7 6 D6 ( R/W ) 5 D5 ( R/W ) 4 D4 ( R/W ) 3 D3 ( R/W ) 2 D2 ( R/W ) 1 D1 ( R/W ) 0 D0 ( R/W )
Address : 000074H
D7 ( R/W )
Initial Value XXXXXXXXB
45
MB90335 Series
* Block Diagram
ICCR EN
I2C enable Clock devide 1
Peripheral clock
5 6 7 8
ICCR CS4 CS3 CS2 CS1 CS0
Clock selector 1 Clock devide 2
2 4 8 16 32 64 128 256 Sync
Generating shift clock
F2MC-16 bus
Clock selector 2 Shift clock edge change timing Bus busy Repeat start Start stop condition detection Error
First Byte
IBSR BB RSC LRB TRX FBT AL IBCR BER BEIE
Last Bit
Send/receive
Arbitration lost detection
SCL0
Interrupt request
INTE INT IBCR SCC MSS ACK GCAA
IRQ
SDA0
Start Master ACK enable
GC-ACK enable
End
Start stop condition generation
IDAR IBSR AAS GCA
Slave Global call Slave address compare
IADR
46
MB90335 Series
9. USB Function
The USB is an interface supporting the USB (Universal Serial Bus) communications protocol. Feature of USB function * Conform to USB 2.0 Full Speed * FULL speed (12 Mbps) is supported. * The device status is auto-answer. * Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16. * Toggle check by data synchronization bit. * Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these three commands can be processed the same way as the class vendor commands). * The class vendor commands can be received as data and responded via firmware. * Supports up to maximum six EndPoints (EndPoint0 is fixed to control transfer). * Two transfer data buffers integrated for each end point (one IN buffer and one OUT buffer for end point 0). * Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0). * Capable of detection of connection and disconnection by monitoring the USB bus power line. * Register list UDC control register (UDCC)
7 6 5 4 USTP ( R/W ) 3 2 1 RFBK ( R/W ) 0 PWC ( R/W )
Address : 0000D0H
RST ( R/W )
RESUM HCONX ( R/W ) ( R/W )
Reserved Reserved
Initial Value 10100000B
( R/W )
( R/W )
EP0 control register (EP0C)
7 6 PKS0 ( R/W ) 5 PKS0 ( R/W ) 4 PKS0 ( R/W ) 3 PKS0 ( R/W ) 2 PKS0 ( R/W ) 1 PKS0 ( R/W ) 0 PKS0 ( R/W )
Address : 0000D2H
Reserved
Initial Value X1000000B
( R/W )
15
14 ()
13 ()
12 ()
11
10
9 STAL ( R/W )
8
Reserved
Address : 0000D3H
()
Reserved Reserved
Initial Value XXXX0000B
( R/W )
( R/W )
( R/W )
EP1 control register (EP1C)
7 6 PKS1 ( R/W ) 5 PKS1 ( R/W ) 4 PKS1 ( R/W ) 3 PKS1 ( R/W ) 2 PKS1 ( R/W ) 1 PKS1 ( R/W ) 0 PKS1 ( R/W )
Address : 0000D4H
PKS1 ( R/W )
Initial Value 00000000B
15
14 TYPE ( R/W )
13 TYPE ( R/W )
12 DIR ( R/W )
11 DMAE ( R/W )
10 NULE ( R/W )
9 STAL ( R/W )
8 PKS1 ( R/W )
Address : 0000D5H
EPEN ( R/W )
Initial Value 01100001B
(Continued)
47
MB90335 Series
EP2/3/4/5 control register (EP2C 0000D6H 0000D8H 0000DAH 0000DCH
7
EP5C)
6 5 4 3 2 1 0
Initial Value 01000000B
Address :
Reserved PKS25 PKS25 PKS25 PKS25 PKS25 PKS25 PKS25
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14 TYPE ( R/W )
13 TYPE ( R/W )
12 DIR ( R/W )
11 DMAE ( R/W )
10 NULE ( R/W )
9 STAL ( R/W )
8
Reserved
Initial Value 01100000B
0000D7H Address : 0000D9H 0000DBH 0000DDH
EPEN ( R/W )
( R/W )
Time stamp register (TMSP)
7 6 TMSP (R) 5 TMSP (R) 4 TMSP (R) 3 TMSP (R) 2 TMSP (R) 1 TMSP (R) 0 TMSP (R)
Address : 0000DEH
TMSP (R)
Initial Value 00000000B
15
14 ()
13 ()
12 ()
11 ()
10 TMSP (R)
9 TMSP (R)
8 TMSP (R)
Address : 0000DFH
()
Initial Value 00000000B
UDC status register (UDCS)
7 6 VON ( R/W ) 5 SUSP ( R/W ) 4 SOF ( R/W ) 3 BRST ( R/W ) 2 WKUP ( R/W ) 1 SETP ( R/W ) 0 CONF ( R/W )
Address : 0000E0H
VOFF ( R/W )
Initial Value 00000000B
Interrupt enable register (UDCIE)
15 14 13 12 11 10 9 8
Address : 0000E1H
VOFFIE VONIE SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) (R) ( R/W )
Initial Value 00000000B
EP0I status register (EP0IS)
7 6 () 5 () 4 () 3 () 2 () 1 () 0 ()
Address : 0000E2H
()
Initial Value XXXXXXXXB
15
14 DRQIIE ( R/W )
13 ()
12 ()
11 ()
10 DRQI ( R/W )
9 ()
8 ()
Address : 0000E3H
BFINI ( R/W )
Initial Value 10XXX1XXB
(Continued)
48
MB90335 Series
(Continued)
EP0O status register (EP0OS)
7 6 SIZE (R) 5 SIZE (R) 4 SIZE (R) 3 SIZE (R) 2 SIZE (R) 1 SIZE (R) 0 SIZE (R)
Address : 0000E4H
()
Initial Value XXXXXXXXB
15
14
13
12 ()
11 ()
10 DRQO ( R/W )
9 SPK ( R/W )
8 ()
Address : 0000E5H
BFINI ( R/W )
DRQOIE SPKIE ( R/W ) ( R/W )
Initial Value 100XX00XB
EP1 status register (EP1S)
7 6 SIZE ( R/W ) 5 SIZE ( R/W ) 4 SIZE ( R/W ) 3 SIZE ( R/W ) 2 SIZE ( R/W ) 1 SIZE ( R/W ) 0 SIZE ( R/W )
Address : 0000E6H
SIZE ( R/W )
Initial Value XXXXXXXXB
15
14 DRQIE ( R/W )
13 SPKIE ( R/W )
12 ()
11 BUSY (R)
10 DRQ ( R/W )
9 SPK ( R/W )
8 SIZE ( R/W )
Address : 0000E7H
BFINI ( R/W )
Initial Value 1000000XB
EP2/3/4/5 status register (EP2S to EP5S) 0000E8H Address : 0000EAH 0000ECH 0000EEH
7 () 6 SIZE ( R/W ) 5 SIZE ( R/W ) 4 SIZE ( R/W ) 3 SIZE ( R/W ) 2 SIZE ( R/W ) 1 SIZE ( R/W ) 0 SIZE ( R/W )
Initial Value XXXXXXXXB
15
14
13
12 ()
11 BUSY (R)
10 DRQ ( R/W )
9 SPK ( R/W )
8 ()
Initial Value 1000000XB
0000E9H BFINI DRQIE SPKIE Address : 0000EBH ( R/W ) ( R/W ) ( R/W ) 0000EDH 0000EFH EP0/1/2/3/4/5 data register (EP0DT to EP5DT) 0000F0H 0000F2H 0000F4H Address : 0000F6H 0000F8H 0000FAH 0000F1H 0000F3H 0000F5H Address : 0000F7H 0000F9H 0000FBH
Initial Value
7 BFDT ( R/W ) 6 BFDT ( R/W ) 5 BFDT ( R/W ) 4 BFDT ( R/W ) 3 BFDT ( R/W ) 2 BFDT ( R/W ) 1 BFDT ( R/W ) 0 BFDT ( R/W )
XXXXXXXXB
Initial Value
15 BFDT ( R/W ) 14 BFDT ( R/W ) 13 BFDT ( R/W ) 12 BFDT ( R/W ) 11 BFDT ( R/W ) 10 BFDT ( R/W ) 9 BFDT ( R/W ) 8 BFDT ( R/W )
XXXXXXXXB
49
MB90335 Series
10. USB Mini-HOST
USB Mini-HOST provides minimal host operations required and is a function that enables data to be transferred to and from Device without PC intervention. Feature of USB Mini-HOST * Automatic detection of Low Speed/Full Speed transfer * Low Speed/Full Speed transfer support * Automatic detection of connection and cutting device * Reset sending function support to USB-bus * Support of IN/OUT/SETUP/SOF token * In-token handshake packet automatic transmission (excluding STALL) * Handshake packet automatic detection at out-token * Supports a maximum packet length of 256 bytes * Error (CRC error/toggle error/time-out) various supports * Wake-Up function support Differences between the USB HOST and USB Mini-HOST HOST Hub support Bulk transfer Transfer Control transfer Interrupt transfer ISO transfer Transfer speed PRE packet support SOF packet support CRC error Toggle error Error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection x : Supported : Not supported Low Speed Full Speed x x Mini-HOST x
50
MB90335 Series
* Register list USB HOST control register 0 (HCONT0)
7 6 5 4 3 DIRE ( R/W ) 2 1 0 HOST ( R/W )
Address : 0000C0H
RWKIRE URIRE CMPIRE CNNIRE ( R/W ) ( R/W ) ( R/W ) ( R/W )
SOFIRE URST ( R/W ) ( R/W )
Initial Value 00000000B
USB HOST control register 1 (HCONT1)
15 14 13 12 11 10 9 8
Address : 0000C1H
Reserved Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY
Initial Value 00000001B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
USB HOST interruption register (HIRQ)
7 6 5 4 3 2 1 DIRQ ( R/W ) 0 SOFIRQ ( R/W )
Address : 0000C2H
TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
USB HOST error status register (HERR)
15 14 13 TOUT ( R/W ) 12 CRC ( R/W ) 11 10 9 HS ( R/W ) 8 HS ( R/W )
Address : 0000C3H
LSTSOF RERR ( R/W ) ( R/W )
TGERR STUFF ( R/W ) ( R/W )
Initial Value 00000011B
USB HOST state status register (HSTATE)
7 6 () 5 4 3 2 1 0
Address : 0000C4H
()
ALIVE CLKSEL SOFBUSY SUSP ( R/W ) ( R/W ) ( R/W ) ( R/W )
TMODE CSTAT (R) (R)
Initial Value XX010010B
USB SOF interruption FRAME comparison register (HFCOMP) Address : 0000C5H
15 14 13 12 11 10 9 8 FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME COMP COMP COMP COMP COMP COMP COMP COMP ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
USB retry timer setting register 0/1/2 (HRTIMER)
7 6 5 4 3 2 1 0
Address : 0000C6H
RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0 RTIMER0
Initial Value 00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
15
14
13
12
11
10
9
8
Address : 0000C7H
RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1 RTIMER1
Initial Value 00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W ) ( R/W ) ( R/W )
7
6 ()
5 ()
4 ()
3 ()
2 ()
1
0
Address : 0000C8H
()
RTIMER2 RTIMER2
Initial Value XXXXXX00B
( R/W )
( R/W )
(Continued)
51
MB90335 Series
(Continued)
USB HOST address register (HADR)
15 14 13 12 11 10 9 8
Address : 0000C9H
()
ADDRESS ADDRESSADDRESSADDRESSADDRESSADDRESSADDRESS
Initial Value X0000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
USB EOF setting register 0/1 (HEOF)
7 6 EOF0 ( R/W ) 5 EOF0 ( R/W ) 4 EOF0 ( R/W ) 3 EOF0 ( R/W ) 2 EOF0 ( R/W ) 1 EOF0 ( R/W ) 0 EOF0 ( R/W )
Address : 0000CAH
EOF0 ( R/W )
Initial Value 00000000B
15
14 ()
13 EOF1 ( R/W )
12 EOF1 ( R/W )
11 EOF1 ( R/W )
10 EOF1 ( R/W )
9 EOF1 ( R/W )
8 EOF1 ( R/W )
Address : 0000CBH
()
Initial Value XX000000B
USB FRAME setting register (HFRAME)
7 6 5 4 3 2 1 0
Address : 0000CCH
FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 FRAME0 ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
15
14 ()
13 ()
12 ()
11 ()
10
9
8
Address : 0000CDH
()
FRAME1 FRAME1 FRAME1
Initial Value XXXXX000B
( R/W )
( R/W )
( R/W )
USB token end point register (HTOKEN)
7 6 5 4 3 2 1 0
Address : 0000CEH
TGGL ( R/W )
TKNEN TKNEN TKNEN ENDPT ENDPT ENDPT ENDPT ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value 00000000B
52
MB90335 Series
11. DTP/external interrupt circuit
Feature of DTP/external interrupt circuit DTP (Data Transfer Peripheral)/external interrupt circuit detects the interrupt request input from the external interrupt input terminal INT7 to INT0, and outputs the interrupt request. * DTP/external interrupt circuit function The DTP/external interrupt function outputs an interrupt request upon detection of the edge or level signal input to the external interrupt input pins (INT7 to INT0). If CPU accept the interrupt request, and if the extended intelligent I/O service (EI2OS) is enabled, branches to the interrupt handling routine after completing the automatic data transfer (DTP function) performed by EI2OS. And if EI2OS is disabled, it branches to the interrupt handling routine without activating the automatic data transfer (DTP function) performed by EI2OS. * Feature of DTP/external interrupt circuit External interrupt Input pin DTP function 8 channels (P60/INT0, P61/INT1, P62/INT2/SIN, P63/INT3/SOT, P64/INT4/SCK, P65/INT5/PWC, P66/INT6/SCL0, P67/INT7/SDA0) The detection level or the type of the edge for each terminals can be set in the request level setting register (ELVR) Input of "H" level/ "L" level/rising edge/falling edge. Interrupt number Interrupt control Interrupt flag Process setting Process #18 (12H) , #20 (14H) , #22 (16H) , #24 (18H) Enabling/Prohibit the interrupt request output using the DTP/interrupt enable register (ENIR) Holding the interrupt source using the DTP/interrupt cause register (EIRR) Prohibit EI2OS (ICR: ISE="0") Branched to the interrupt handling routine Enable EI2OS (ICR: ISE="1") After an automatic data transfer by EI2OS, Branched to the interrupt handling routine
Interrupt source
* Register list Interrupt/DTP enable register (ENIR)
7 6 EN6 (R/W) 5 EN5 (R/W) 4 EN4 (R/W) 3 EN3 (R/W) 2 EN2 (R/W) 1 EN1 (R/W) 0 EN0 (R/W)
Address : 00003CH
EN7 (R/W)
Initial Value 00000000B
Interrupt/DTP source register (EIRR)
15 14 ER6 (R/W) 13 ER5 (R/W) 12 ER4 (R/W) 11 ER3 (R/W) 10 ER2 (R/W) 9 ER1 (R/W) 8 ER0 (R/W)
Address : 00003DH
ER7 (R/W)
Initial Value 00000000B
Request level setting register (ELVR)
7 6 LA3 (R/W) 14 LA7 (R/W) 5 LB2 (R/W) 13 LB6 (R/W) 4 LA2 (R/W) 12 LA6 (R/W) 3 LB1 (R/W) 11 LB5 (R/W) 2 LA1 (R/W) 10 LA5 (R/W) 1 LB0 (R/W) 9 LB4 (R/W) 0 LA0 (R/W) 8 LA4 (R/W)
Address : 00003EH
LB3 (R/W) 15
Initial Value 00000000B
Address : 00003FH
LB7 (R/W)
Initial Value 00000000B
53
MB90335 Series
* Block Diagram Request level setting register (ELVR)
LB7 LA7 2 LB6 LA6 2 LB5 LA5 2 LB4 LA4 2 LB3 LA3 2 LB2 LA2 2 LB1 LA1 2 LB0 LA0 2
Pin
P67/INT7 SDA0
Selector
DTP/external interrupt input detection circuit
Selector
Pin
P60/INT0
Pin
P66/INT6 SCL0
Selector
Selector
Pin
P61/INT1
Internal data bus
Pin
P65/INT5 PWC
Selector
Selector
Pin
P62/INT2 SIN
Pin
P64/INT4 SCK DTP/interrupt source register (EIRR)
Selector
Selector
Pin
P63/INT3 SOT
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
Interrupt request signal
#18(12H) #20(14H) #22(16H)
DTP/interrupt enable register (ENIR)
#24(18H)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
* : Interrupt number
54
MB90335 Series
12. Interrupt controller
The interrupt control register is located inside the interrupt controller, it exists for every I/O having an interrupt function. This register has the following functions. * Setting of the interrupt levels of relevant peripheral * Register list Interrupt control register Address ICR01 : 0000B1H ICR03 : 0000B3H ICR05 : 0000B5H ICR07 : 0000B7H ICR09 : 0000B9H ICR11 : 0000BBH ICR13 : 0000BDH ICR15 : 0000BFH Read/Write Initial Value ICR00 : 0000B0H ICR02 : 0000B2H ICR04 : 0000B4H ICR06 : 0000B6H ICR08 : 0000B8H ICR10 : 0000BAH ICR12 : 0000BCH ICR14 : 0000BEH Read/Write Initial Value
15 ICS3 (W) (0)
14 ICS2 (W) (0)
13 ICS1 (W) (0)
12 ICS0 (W) (0)
11 ISE ( R/W ) (0)
10 IL2 ( R/W ) (1)
9 IL1 ( R/W ) (1)
8 IL0 ( R/W ) (1)
ICR01, 03, 05, 07, 09, 11, 13, 15
Address
7 ICS3 (W) (0)
6 ICS2 (W) (0)
5 ICS1 (W) (0)
4 ICS0 (W) (0)
3 ISE ( R/W ) (0)
2 IL2 ( R/W ) (1)
1 IL1 ( R/W ) (1)
0 IL0 ( R/W ) (1)
ICR00, 02, 04, 06, 08, 10, 12, 14
Note : Do not access interrupt control registers using any read modify write instruction because it causes a malfunction. * Block Diagram
3 I L2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 I L1 IL 0
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
32
Interrupt request (peripheral resource)
F2MC-16LX bus
Determine priority of interrupt
3
(CPU) Interrupt level
55
MB90335 Series
13. DMAC
DMAC is simple DMA with the function equal with EI2OS. It has 16 channels DMA transfer channels with the following features. * Performs automatic data transfer between the peripheral resource (I/O) and memory * The program execution of CPU stops in the DMA startup * Capable of selecting whether to increment the transfer source and destination addresses * DMA transfer is controlled by the DMA enable register, DMA stop status register, DMA status register and descriptor * A STOP request is available for stopping DMA transfer from the resource * Upon completion of DMA transfer, the flag bit corresponding to the transfer completed channel in the DMA status register is set and a termination interrupt is output to the transfer controller. * Register list DMA enable register higher (DERH)
15 14 EN14 ( R/W ) 13 EN13 ( R/W ) 12 EN12 ( R/W ) 11 EN11 ( R/W ) 10 EN10 ( R/W ) 9 EN9 ( R/W ) 8 EN8 ( R/W )
Address : 0000ADH
EN15 ( R/W )
Initial Value 00000000B
DMA enable register lower (DERL)
7 6 EN6 ( R/W ) 5 EN5 ( R/W ) 4 EN4 ( R/W ) 3 EN3 ( R/W ) 2 EN2 ( R/W ) 1 EN1 ( R/W ) 0 EN0 ( R/W )
Address : 0000ACH
EN7 ( R/W )
Initial Value 00000000B
DMA stop status register (DSSR) Address : 0000A4H
7 STP7 STP15 ( R/W ) 6 STP6 STP14 ( R/W ) 5 STP5 STP13 ( R/W ) 4 STP4 STP12 ( R/W ) 3 STP3 STP11 ( R/W ) 2 STP2 STP10 ( R/W ) 1 STP1 STP9 ( R/W ) 0 STP0 STP8 ( R/W )
Initial Value 00000000B *
DMA status register higher (DSRH)
15 14 DTE14 ( R/W ) 13 DTE13 ( R/W ) 12 DTE12 ( R/W ) 11 DTE11 ( R/W ) 10 DTE10 ( R/W ) 9 DTE9 ( R/W ) 8 DTE8 ( R/W )
Address : 00009DH
DTE15 ( R/W )
Initial Value 00000000B
DMA status register lower (DSRL)
7 6 DTE6 ( R/W ) 5 DTE5 ( R/W ) 4 DTE4 ( R/W ) 3 DTE3 ( R/W ) 2 DTE2 ( R/W ) 1 DTE1 ( R/W ) 0 DTE0 ( R/W )
Address : 00009CH
DTE7 ( R/W )
Initial Value 00000000B
DMA descriptor channel specification register (DCSR)
7 6 5 4 3 2 1 0 DCSR0 ( R/W )
Address : 00009BH
STP ( R/W )
Reserved Reserved Reserved DCSR3 DCSR2 DCSR1
Initial Value 00000000B
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
( R/W )
* : The DSSR is lower when the STP bit of DCSR in the DSSR is 0. The DSSR is upper when the STP bit of DCSR in the DSSR is 1.
(Continued)
56
MB90335 Series
(Continued)
DMA buffer address pointer lower 8 bit (DBAPL)
7 6 5 4 3 2 1 0
Address : 007920H
DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL DBAPL ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value XXXXXXXXB
DMA buffer address pointer middle 8 bit (DBAPM)
15 14 13 12 11 10 9 8
Address : 007921H
DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM DBAPM ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value XXXXXXXXB
DMA Buffer address pointer higher 8 bit (DBAPH)
7 6 5 4 3 2 1 0
Address : 007922H
DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH DBAPH ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W ) ( R/W )
Initial Value XXXXXXXXB
DMA control register (DMACS)
15 14 RDY1 ( R/W ) 13 BYTEL ( R/W ) 12 IF ( R/W ) 11 BW ( R/W ) 10 BF ( R/W ) 9 DIR 8 SE
Address : 007923H
RDY2 ( R/W )
Initial Value XXXXXXXXB
( R/W ) ( R/W )
DMA I/O register address pointer lower 8 bit (DIOAL)
7 6 A06 ( R/W ) 5 A05 ( R/W ) 4 A04 ( R/W ) 3 A03 ( R/W ) 2 A02 ( R/W ) 1 A01 ( R/W ) 0 A00 ( R/W )
Address : 007924H
A07 ( R/W )
Initial Value XXXXXXXXB
DMA I/O register address pointer higher 8 bit (DIOAH)
15 14 A14 ( R/W ) 13 A13 ( R/W ) 12 A12 ( R/W ) 11 A11 ( R/W ) 10 A10 ( R/W ) 9 A09 ( R/W ) 8 A08 ( R/W )
Address : 007925H
A15 ( R/W )
Initial Value XXXXXXXXB
DMA data counter lower 8 bit (DDCTL)
7 6 B06 ( R/W ) 5 B05 ( R/W ) 4 B04 ( R/W ) 3 B03 ( R/W ) 2 B02 ( R/W ) 1 B01 ( R/W ) 0 B00 ( R/W )
Address : 007926H
B07 ( R/W )
Initial Value XXXXXXXXB
DMA data counter higher 8 bit (DDCTH)
15 14 B14 ( R/W ) 13 B13 ( R/W ) 12 B12 ( R/W ) 11 B11 ( R/W ) 10 B10 ( R/W ) 9 B09 ( R/W ) 8 B08 ( R/W )
Address : 007927H
B15 ( R/W )
Initial Value XXXXXXXXB
Note : The above register is switched for each channel depending on the DCSR.
57
MB90335 Series
14. Address matching detection function
When the address is equal to the value set in the address detection register, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code (01H). As a result, the CPU executes the INT9 instruction when executing the set instruction. By performing processing by the INT#9 interrupt routine, the program patch function is enabled. Two address detection registers are provided, for each of which there is an interrupt enable bit. When the address matches the value set in the address detection register with the interrupt enable bit set to 1, the instruction code to be read into the CPU is forcibly replaced with the INT9 instruction code. * Register list * Program address detect register 0 to 2 (PADR0) PADR0 (lower) 7 6 5 Address : 001FF0H
(R/W) (R/W) (R/W)
4
3
2
1
0
Initial Value XXXXXXXXB
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
PADR0 (middle) Address : 001FF1H
15
14
13
12
11
10
9
8
Initial Value XXXXXXXXB
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
PADR0 (higher) Address : 001FF2H
7
6
5
4
3
2
1
0
Initial Value XXXXXXXXB
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
* Program address detect register 3 to 5 (PADR1) PADR1 (lower) 15 14 13 Address : 001FF3H
(R/W) (R/W) (R/W)
12
11
10
9
8
Initial Value XXXXXXXXB
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
PADR1 (middle) Address : 001FF4H
7
6
5
4
3
2
1
0
Initial Value XXXXXXXXB
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
PADR1 (higher) Address : 001FF5H
15
14
13
12
11
10
9
8
Initial Value XXXXXXXXB
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
* Program address detect control status register (PACSR) PACSR 7 6 5 4 3 Address : 00009EH Reserved Reserved Reserved Reserved AD1E
(R/W) (R/W) (R/W) (R/W) (R/W)
2
Reserved
1 AD0E (R/W)
0
Reserved
Initial Value 00000000B
(R/W)
(R/W)
R/W : Readable and Writable X : Undefined
58
MB90335 Series
15. Delay interrupt generator module
* The delay interrupt generation module is a module that generates interrupts for switching tasks. A hardware interrupt can be generated by software. * Function of delay interrupt generator module Function and control * Setting the R0 bit in the delayed interrupt request generate/cancel register to 1 (DIRR: R0 = 1) generates a interrupt request. * Setting the R0 bit in the delayed interrupt request generate/cancel register to 0 (DIRR: R0 = 0) cancels the interrupt request. * No setting of permission register is provided. * Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0) * Not ready for expanded intelligent I/O service (EI2OS).
Interrupt source
Interrupt control Interrupt flag EI2OS support * Block Diagram
Internal data bus

R0
S Interrupt request
Delayed Interrupt source/release register (DIRR)
R Latch
: Undefined bit
Interrupt request signal
59
MB90335 Series
16. ROM mirroring function selection module
* The ROM mirror function select module can make a setting so that ROM data located in bank FF can be read by accessing bank 00. * ROM mirroring function selection module Description Mirror setting address Interrupt source EI OS support * Block Diagram ROM mirror function selection register (ROMM)

Reserved
2
FFFFFFH to FF8000H in the FF bank can be read through 00FFFFH to 008000H in the 00 bank. * None * Not ready for extended intelligent I/O service (EI2OS).
MI
Address Internal data bus Address area FF bank 00 bank
Data
ROM
60
MB90335 Series
17. Low power consumption (standby) mode
* The F2MC-16LX can be set to save power consumption by selecting and setting the low power consumption mode. * CPU operation mode and functional description CPU Operation operating clock mode Normally run Sleep PLL clock
Description
The CPU and peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency. Only peripheral resources operate at the clock frequency obtained by PLL multiplication of the oscillator clock (HCLK) frequency.
Time-base Only the time-base timer operates at the clock frequency obtained by PLL timer multiplication of the oscillator clock (HCLK) frequency. Stop normally run Sleep The CPU and peripheral resources are suspended with the oscillator clock stopped. The CPU and peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two. Only peripheral resources operate at the clock frequency obtained by dividing the oscillator clock (HCLK) frequency by two.
Main clock
Time-base Only the time-base timer operates at the clock frequency obtained by dividing the timer oscillator clock (HCLK) frequency by two. Stop The CPU and peripheral resources are suspended with the oscillator clock stopped. The halved or PLL-multiplied oscillator clock (HCLK) frequency is used for operation while being decimated in a certain period.
CPU intermittent operation mode * Register list
Normally run
Lowe power consumption mode control register (LPMCR)
7 6 SLP (W) 5 SPL ( R/W ) 4 RST (W) 3 TMD ( R/W ) 2 CG1 ( R/W ) 1 CG0 ( R/W ) 0
Reserved
Address : 0000A0H
STP (W)
Initial Value 00011000B
( R/W )
61
MB90335 Series
18. Clock
The clock generator controls the internal clock as the operating clock for the CPU and peripheral resources. The internal clock is referred to as machine clock whose one cycle is defined as machine cycle. The clock based on source oscillation is referred to as oscillator clock while the clock based on internal PLL oscillation as PLL clock. * Register list Clock selection register (CKSCR)
15 14 MCM (R) 13 WS1 ( R/W ) 12 WS0 ( R/W ) 11 SCS ( R/W ) 10 MCS ( R/W ) 9 CS1 ( R/W ) 8 CS0 ( R/W )
Address : 0000A1H
SCM (R)
Initial Value 11111100B
62
MB90335 Series
19. 512 Kbits flash memory
The description that follows applies to the flash memory built in the MB90F334; it is not applicable to evaluation ROM or masked ROM. The method of data write/erase to flash memory is following three types. * Parallel writer * Serial dedicated writer * Write/erase by executing program * Description of 512 Kbits flash memory 512 Kbits flash memory is located in FFH bank in the CPU memory map. Function of flash memory interface circuit enables read and program access from CPU. Write/erase to flash interface is executed by instruction from CPU via flash memory interface, so rewrite of program and data is carried on in the mounting state effectively. Data can be reprogrammed not only by program execution in existing RAM but by program execution in flash memory by dual operation. The different banks (the upper and lower banks) can be used to execute an erase/ program and a read concurrently. Also, erase/write and read in the defferent bank (Upper Bank/Lower Bank) is executed simultaneously. * Features of 512 Kbits flash memory * Sector configuration : 64 Kwords x 8 bits/32 words x 16 bits (4K x 4 + 16K x 2 + 4K x 4) * Simultaneous execution of erase/write and read by 2-bank configuration * Automatic program algorithm (Embeded AlgorithmTM*) * Built-in deletion pause/deletion resume function * Detection of programming/erasure completion using data polling and the toggle bit * At least 10,000 times guaranteed * Minimum flash read cycle time : 2 machine cycles * : Embedded AlgorithmTM is a trade mark of Advanced Micro Devices Inc. Note : The read function of manufacture code and device coad is not including. Also, these code is not accessed by the command. * Flash write/erase * Flash memory can not execute write/erase and read by the same bank simultaneously. * Data can be programmed/deleted into and erased from flash memory by executing either the program residing in the flash memory or the one copied to RAM from the flash memory.
63
MB90335 Series
* Sector configuration of flash memoly Flash Memory CPU address Writer address *
SA0 (4 Kbyte) SA1 (4 Kbyte) FF0000H FF0FFFH FF1000H FF1FFFH FF2000H SA2 (4 Kbyte) SA3 (4 Kbyte) SA4 (16 Kbyte) SA5 (16 Kbyte) FF2FFFH FF3000H FF3FFFH FF4000H FF7FFFH FF8000H FFBFFFH FFC000H SA6 (4 Kbyte) SA7 (4 Kbyte) SA8 (4 Kbyte) FFCFFFH FFD000H FFDFFFH FFE000H FFEFFFH FFF000H SA9 (4Kbyte) FFFFFFH 70000H 70FFFH 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H 78FFFH 7CFFFH 7D000H 7DFFFH 7E000H 7EFFFH 7F000H 7FFFFH Upper Bank 7C000H Lower Bank 71000H
* : Flash memory writer address indicates the address equivalent to the CPU address when data is written to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.
64
MB90335 Series
* Register list Flash memory control register (FMCS)
7 6 RDYINT ( R/W ) 5 WE ( R/W ) 4 RDY (R) 3
Reserved
2
1
0 LPM0 ( R/W )
Address : 0000AEH
INTE ( R/W )
LPM1 Reserved ( R/W ) (W)
Initial Value 000X0000B
(W)
Flash memory program control register (FWR0)
7 6 SA6E ( R/W ) 5 SA5E ( R/W ) 4 SA4E ( R/W ) 3 SA3E ( R/W ) 2 SA2E ( R/W ) 1 SA1E ( R/W ) 0 SA0E ( R/W )
Address : 00790CH
SA7E ( R/W )
Initial Value 00000000B
Flash memory program control register (FWR1)
15 14 ( R/W ) 13 ( R/W ) 12 ( R/W ) 11 ( R/W ) 10 ( R/W ) 9 SA9E ( R/W ) 0 SA8E ( R/W )
Address : 00790DH
( R/W )
Initial Value 00000000B
Sector conversion setting register (SSR0)
7 6 ( R/W ) 5 () 4 () 3 () 2 () 1 () 0 SEN0 ( R/W )
Address : 00790EH
( R/W )
Initial Value 00XXXXX0B
When writing to SSR0 register, write "0" except for SEN0.
65
MB90335 Series
* Standard configuration for Fujitsu standard serial on-board writing The flash microcontroller programmer (AF220/AF210/AF120/AF110) made by Yokogawa Digital Computer Corp. is used for Fujitsu standard serial onboard writing.
Host interface cable (AZ201)
General-purpose common cable (AZ210)
RS232C
Flash microcontroller programmer + Memory card
CLK synchronous serial
MB90F337 user system
Can operate standalone
Note : Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the flash microcontroller programmer (AF220, AF210, AF120 and AF110) , general-purpose common cable for connection (AZ210) and connectors. * Pins Used for Fujitsu Standard Serial On-board Programming Pin Function Description The device enters the serial program mode by setting MD2 = 1, MD1 = 1 and MD0 = 0. Because the internal CPU operation clock is set to be the 1 multiplication PLL clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. Input a Low level to P60 and a High level to P61. UART0 is used as CLK synchronous mode. In write mode, the pins used for the UART0 CLK synchronous mode are SIN0, SOT0, and SCK0. When supplying the write voltage (MB90F337 : 3.3 V0.3 V) from the user system, connection with the flash microcontroller programmer is not necessary. When connecting, do not short-circuit with the user power supply. Share GND with the flash microcontroller programmer. MD2, Mode input pin MD1, MD0 X0, X1 P60, P61 RST SIN0 SOT0 SCK0 Oscillation pin Write program start pins Reset input pin Serial data input pin Serial data output pin Serial clock input pin
VCC
Power source input pin
VSS
GND Pin
66
MB90335 Series
The control circuit shown in the diagram is required for using the P60, P61, SIN0, SOT0 and SCK0 pins on the user system. Isolate the user circuit during serial on-board writing, with the /TICS signal of the flash microcontroller programmer.
AF220/AF210/AF120/AF110 Write control pin
10 k
MB90F337 write control pin
AF220/AF210/AF120/AF110 /TICS pin User Control circuit The MB90F337 serial clock frequency that can be input is determined by the following expression * Use the flash microcontroller programmer to change the serial clock input frequency setting depending on the oscillator clock frequency to be used. Imputable serial clock frequency = 0.125 x oscillation clock frequency. * Maximum serial clock frequency Oscillation clock frequency At 6 MHz Maximum serial clock frequency acceptable to the microcontroller 750 kHz Maximum serial clock frequency that can be set with the AF220/AF210/ AF120/AF110 500 kHz Maximum serial clock frequency that can be set with the AF200 500 kHz
* System configuration of the flash microcontroller programmer (AF220/AF210/AF120/AF110) (made by Yokogawa
Digital Computer Corp.)
Part number AF220/AC4P Unit AF210/AC4P AF120/AC4P AF110/AC4P AZ221 AZ210 FF201 AZ290 /P2 Model with internal Ethernet interface Standard model
Function /100 V to 220 V power adapter /100 V to 220 V power adapter /100 V to 220 V power adapter /100 V to 220 V power adapter
Single key internal Ethernet interface mode Single key model PC/AT RS232C cable for writer Standard target probe (a) length : 1 m
Control module for Fujitsu F2MC-16LX flash microcontroller control module Remote controller 2 MB PC Card (option) FLASH memory capacity to respond to 128 KB
/P4 4 MB PC Card (option) FLASH memory capacity to respond to 512 KB Contact to : Yokogawa Digital Computer Corp. TEL : (81)-42-333-6224 Note : The AF200 flash micon programmer is a retired product, but it can be supported using control module FF201.
67
MB90335 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS - 0.3 VSS - 0.3 Input voltage VI VSS - 0.3 - 0.5 Output voltage L level maximum output current L level average output current L level maximum total output current L level average total output current H level maximum output current H level average output current H level maximum total output current H level average total output current Power consumption Operating temperature Storage temperature VO IOL1 IOL2 IOLAV IOL IOLAV IOH1 IOH2 IOHAV IOH IOHAV Pd TA Tstg VSS - 0.3 - 0.5 - 40 - 55 - 55 Max VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.5 VSS + 4.0 VSS + 4.5 10 43 3 60 30 - 10 - 43 -3 - 60 - 30 351 + 85 + 150 + 125 (VCC = 3.3 V, VSS = 0.0 V) Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C C USB I/O *4 Target value *4 Other than USB I/O*2 USB I/O*2 *3 *1 Nch0.D (Withstand voltage I/O of 5 V) USB I/O *1 USB I/O Other than USB I/O*2 USB I/O*2 *3 Remarks
Parameter Power supply voltage
Symbol VCC
*1 : VI and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *2 : A peak value of an applicable one pin is specified as a maximum output current. *3 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *4 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 68
MB90335 Series
2. Recommended Operating Conditions
Value Min 3.0 Power supply voltage VCC VIH Input H level voltage VIHS VIHM VIHUSB VIL Input L level voltage VILS VILM VILUSB Differential input sensitivity Differential common mode input voltage range Series resistance Operating temperature VDI 2.7 1.8 0.7 VCC 0.8 VCC VCC - 0.3 2.0 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS 0.2 Max 3.6 3.6 3.6 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.8 2.5 30 + 85 + 70
(VSS = 0.0 V) Unit V V V V V V V V V V V V Remarks At normal operation (At USB is used) At normal operation (At USB is unused) Hold state of stop operation CMOS input pin CMOS hysteresis input pin MD input pin USB input pin CMOS input pin CMOS hysteresis input pin MD input pin USB input pin USB input pin
Parameter
Symbol
VCM RS TA
0.8 25 - 40 0
V C C
USB input pin Recommended value = 27 at using USB At USB is unused At USB is used
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB90335 Series
3. DC Characteristics
Parameter Output H level voltage Output L level voltage Symbol Pin name
(TA = - 40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Conditions Value Min
VCC - 0.5
Typ 50 0.1
Max Vcc 3.6
Vss + 0.4
Unit Remarks
VOH
Output pin of other than P60 to P67, HVP IOH = -4.0 mA , HVM, DVP DVM , HVP HVM, DVP DVM RL = 15 k 5% , , Output pin of other than HVP HVM, DVP IOL = 4.0 mA , , DVM HVP HVM, DVP DVM RL = 1.5 k 5% , , Output pin of other VCC = 3.3 V, than P60 to P67, HVP , Vss < VI < VCC HVM, DVP DVM , HVP HVM, DVP DVM , , VCC = 3.3 V, Ta = + 25 C VCC = 3.3 V, Internal frequency 24 MHz, At normal operating VCC = 3.3 V, Internal frequency 24 MHz, At normal operating VCC = 3.3 V, Internal frequency 24 MHz, At normal operating VCC P00 to P07, P10 to P17
V V V V A A k A
At USB operating mA Max 90 mA (Target) At nonoperating mA USB (USTP = 0) At nonoperating mA USB (USTP = 1)
2.8 Vss 0 - 10 -5 25
VOL
0.3 10 5 100 10
Input leak current Pull-up resistor Open drain output current
IIL
RPULL
ILIOD P60 to P67
TBD
ICC
70
TBD
Power supply current
ICCS
VCC = 3.3 V, Internal frequency 24 MHz, At sleep mode VCC = 3.3 V, Internal frequency 24 MHz, At timer mode VCC = 3.3 V, Internal frequency 3 MHz, At timer mode Ta = +25 C, At Stop mode
27
mA
3.5
mA
ICTS
25
1 1 5 50
15 100
mA A pF k
ICCH Input capacitance Pull-up resistor CIN Rup Other than Vcc and Vss RST

Note : P60 to P67 are N-ch open-drain pins usually used as CMOS. 70
MB90335 Series
4. AC Characteristics
(1) Clock input timing Symbol fCH tHCYL PWH PWL tcr tcf fCP tCP Pin name X0, X1 X0, X1 X0 X0 (TA = -40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Value Min 6 166.7 10 3 42 Typ 6 166.7 Max 24 41.7 5 24 333 Unit Remarks
Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time
MHz External crystal oscillation MHz External clock input ns ns ns ns External crystal oscillation External clock input A reference duty ratio is 30% to 70%. At external clock
MHz At main clock is used ns At main clock is used
* Clock timing
tHCYL 0.8 VCC
X0
0.2 VCC PWH tcf PWL tcr
71
MB90335 Series
* PLL operation guarantee range Relation between internal operation clock frequency and power supply voltage PLL operation guarantee range Power supply voltage VCC (V)
3.6
3.0 2.7
Normal operation assurance range
3 6 12 24
Internal clock fCP (MHz) * : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V. Relation between oscillation frequency and internal operation clock frequency
24
Multiply by 4
Internal clock fCP (MHz)
Multiply by 2
12
External clock
6
Multiply by 1
3
6
24
Oscillation clock FC (MHz) The AC standards provide that the following measurement reference voltages. * Output signal waveform * Input signal waveform Hysteresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Hysteresis input/other than MD input pin
0.7 VCC 0.3 VCC
72
MB90335 Series
(2) Reset Symbol Pin name Conditions
(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Value Min Max Unit Remarks At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode At stop mode
Parameter
Reset input time
500 tRSTL RST Oscillation time of oscillator* + 500 ns
ns
s
* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a FAR/ceramic oscillator, and 0 milliseconds on an external clock. * During normal operation, in time-base timer mode, in main sleep mode and in PLL sleep mode
tRSTL
RST
0.2 VCC 0.2 VCC
* In stop mode
tRSTL
RST
0.2 VCC 0.2 VCC
90% of amplitude
X0
Internal operation clock
Oscillation time of oscillator
500 ns
Oscillation stabilization wait time
Execute instruction Internal reset
73
MB90335 Series
(3) Power-on reset
(TA = -40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Symbol tR tOFF Pin name VCC VCC Conditions Value Min 1 Max 30 Unit ms ms For repeated operation Remarks
Parameter Power supply rising time Power supply shutdown time
Notes : * VCC must be lower than 0.2 V before the power supply is turned on. * The above standard is a value for performing a power - on reset. * In the device, there are internal registers which is initialized only by a power-on reset. When the initial ization of these items is expected, turn on the power supply according to the standards.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms or less.
3.0 V VSS
RAM data hold
74
MB90335 Series
(4) UART0, UART1 I/O extended serial timing Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
(TA = -40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Conditions Value Min 8 tCP Internal shiftc lock Mode output pin is CL = 80 pF + 1 TTL - 80 100 60 4 tCP 4 tCP External shift clock Mode output pin is CL = 80 pF + 1 TTL 60 60 Max 80 150 Unit Remarks ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock H pulse width Serial clock L pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Pin name SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx, SINx SCKx, SINx SCKx SOTx SCKx SINx SCKx SINx
Notes : * AC rating in CLK synchronous mode. * CL is a load capacitance value on pins for testing. * tCP is the machine cycle period (unit : ns) . * Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
75
MB90335 Series
(5) I2C timing Symbol fSCL tBUS tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO Pin Condiname tions
(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Value Min 0 4.7 4.0 4.7 4.0 4.7 0 40 4.0 Max 100 1000 300 Unit kHz s s s s s s ns ns ns s The first clock pulse is generated immediately after the period. Remarks
Parameter SCL clock frequency Bus-free time between stop and start conditions Hold time (resend) start SCL clock "L" status hold time SCL clock "H" status hold time Resend start condition setup time Data hold time Data set-up time SDA and SCL signal rise time SDA and SCL signal fall time Stop condition setup time
0.8 VCC
SDA
tBUS
0.2 VCC tLOW tR tHIGH tF tHDSTA
0.8 VCC
SCL
0.2 VCC
tHDSTA
tHDDAT fSCL
tSUDAT
tSUSTA
tSUSTO
76
MB90335 Series
(6) Timer Input Timing
(TA = -40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Symbol tTIWH tTIWL Pin name PWC Conditions Value Min 4 tCP Max Unit ns Remarks
Parameter Input pulse width
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
PWC
tTIWH tTIWL
(7) Timer output timing Symbol tTO
(TA = -40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Pin name PPGx Conditions Value Min 30 Max Unit ns Remarks
Parameter CLK TOUT change time PPG0 to PPG3 change time
CLK
2.4 V
tTO
PPGx
2.4 V 0.8 V
(8) Trigger Input Timing
(TA = -40 C to +85 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Symbol tTRGH tTRGL Pin name INTx Conditions Value Min 5 tCP 1 Max Unit ns s Remarks At normal operating At Stop mode
Parameter Input pulse width
0.8 VCC
0.8 VCC 0.2 VCC 0.2 VCC
INTx
tTRGH tTRGL
77
MB90335 Series
5. USB characteristics
Sym bol VIH VIL VDI VOH VOL VCRS tFR tLR tFF tLF tRFM tRLM ZDRV
(TA = 0 C to +70 C, VCC = 3.3 V 0.3 V, VSS = 0.0 V) Symbol Value Min 2.0 0.2 0.8 2.8 0.0 1.3 4 75 4 75 90 80 28 Max 0.8 2.5 3.6 0.3 2.0 20 300 20 300 111.11 125 44 Unit V V V V V V V ns ns ns ns % % Full Speed Low Speed Full Speed Low Speed (TFR/TFF) (TLR/TLF) Including Rs = 27 IOH = -200 A IOL = 2 mA Remarks
Parameter
Input High level voltage Input characteristics Input Low level voltage Differential input sensitivity Output High level voltage Output Low level voltage Cross over voltage Rise time Output characteristics Fall time Rising/falling time matching Output registance * Data signal timing (Full Speed) Rise time
DVP/HVP DVM/HVM
Vcrs 10% 90%
Differential common mode range VCM
Fall time
90% 10%
tFR
tFF
* Data signal timing (Low Speed)
Rise time
HVP HVM
Vcrs 10% 90%
Fall time
90% 10%
tLR
tLF
78
MB90335 Series
* Load condition (Full Speed)
RS = 27
Testing point
CL = 50 pF
DVP/HVP
DVM/HVM
RS = 27
Testing point
CL = 50 pF
* Load condition (Low Speed)
RS = 27
Testing point
HVP
CL = 50 pF 150 pF RS = 27
Testing point
HVM
CL = 50 pF 150 pF
79
MB90335 Series
s ORDERING INFORMATION
* MB90335 Series Part number MB90F337PFM MB90337PFM Package 64-pin plastic LQFP (FPT-64P-M09) Remarks
80
MB90335 Series
s PACKAGE DIMENSION
64-pin plastic LQFP (FPT-64P-M09)
14.000.20(.551.008)SQ
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
* 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches) Note : The values in parentheses are reference values.
81
MB90335 Series
MEMO
82
MB90335 Series
MEMO
83
MB90335 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/
North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94088-3470, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fmk.fujitsu.com/
F0312 (c) FUJITSU LIMITED Printed in Japan

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